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AT89C51CC03U-RDTIM 数据表(PDF) 147 Page - ATMEL Corporation |
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AT89C51CC03U-RDTIM 数据表(HTML) 147 Page - ATMEL Corporation |
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147 / 195 page  147 AT89C51CC03 4182I–CAN–06/05 PCA Registers Table 95. CMOD Register CMOD (S:D9h) PCA Counter Mode Register Reset Value = 00XX X000b 76 543 210 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description 7CIDL PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. 6WDTE WatchDog Timer Enable Clear to disable WatchDog Timer function on PCA Module 4, Set to enable it. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2CPS1 EWC Count Pulse Select bits CPS1 CPS0 Clock source 0 0 Internal Clock, FPca/6 0 1 Internal Clock, FPca/2 1 0 Timer 0 overflow 1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4) 1CPS0 Reserved The value read from this bit is indeterminate. Do not set this bit. 0ECF Enable PCA Counter Overflow Interrupt bit Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt. |
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