AT89C51CC03U-RDTIM datasheet(154/195 Pages) ATMEL

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154

AT89C51CC03

4182I–CAN–06/05

ADC Converter

Operation

A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).

After completion of the A/D conversion, the ADSST bit is cleared by hardware.

The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is

available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is

set, an interrupt occur when flag ADEOC is set (see Figure 76). Clear this flag for re-

arming the interrupt.

The bits SCH0 to SCH2 in ADCON register are used for the analog input channel

selection.

Table 102. Selected Analog input

Voltage Conversion

When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If

the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between

VAREF and VAGND are a straight-line linear conversion. All other voltages will result in

3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN should not exceed VAREF absolute maximum range! (See section

“AC-DC”)

Clock Selection

The ADC clock is the same as CPU.

The maximum clock frequency is defined in the DC parameters for A/D converter. A

prescaler is featured (ADCCLH) to generate the ADC clock from the oscillator

frequency.

FADC = Fperiph / 4 (or 2 in X2 mode) x PRS

if PRS = 0 then FADC = Fperiph / 64

if PRS > 0 then FADC = Fperiph / 2 x PRS

SCH2

SCH1

SCH0

Selected Analog input

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AT89C51CC03U-RDTIM 数据表(PDF) 154 Page - ATMEL Corporation

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