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AT89C51CC03U-RDTIM 数据表(PDF) 181 Page - ATMEL Corporation |
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AT89C51CC03U-RDTIM 数据表(HTML) 181 Page - ATMEL Corporation |
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181 / 195 page  181 AT89C51CC03 4182I–CAN–06/05 Timings Test conditions: capacitive load on all pins= 60 pF. Note: 1. Value of this parameter depends on prescacler ratio defined in bits 0,1 and 7 of SCON Register.In the above table, the ratio used is 4. As it can be set also to 8, 16, 32, 64 or 128, the factor of T PER must be changed according to the new ratio.E.g. 2TPER-20ns(1) will be changed to 4TPER-20ns(1) if the prescaler ratio equals 8. Table 1. SPI Interface Master AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85°C Symbol Parameter Min Max Unit Slave Mode TCHCH Clock Period 6(1) TPER TCHCX Clock High Time 3(1) TPER TCLCX Clock Low Time 3(1) TPER TSLCH, TSLCL SS Low to Clock edge 4TPER-20ns (1) ns TIVCL, TIVCH Input Data Valid to Clock Edge 50 ns TCLIX, TCHIX Input Data Hold after Clock Edge 50 ns TCLOV, TCHOV Output Data Valid after Clock Edge 50 ns TCLOX, TCHOX Output Data Hold Time after Clock Edge 0 ns TCLSH, TCHSH SS High after Clock Edge 4TPER+20ns (1) ns TSLOV SS Low to Output Data Valid 4TPER+20ns (1) ns TSHOX Output Data Hold after SS High 2TPER+100ns (1) ns TSHSL SS High to SS Low 2TPER+120ns (1) TOLOH Output Rise time 100 ns TOHOL Output Fall Time 100 ns Master Mode TCHCH Clock Period 4(1) TPER TCHCX Clock High Time 2TPER-20ns (1) TPER TCLCX Clock Low Time 2TPER-20ns (1) TPER TIVCL, TIVCH Input Data Valid to Clock Edge 50 ns TCLIX, TCHIX Input Data Hold after Clock Edge 0 ns TCLOV, TCHOV Output Data Valid after Clock Edge 20 ns TCLOX, TCHOX Output Data Hold Time after Clock Edge 0 ns TCLCH Output Data Rise time 100 ns TCHCL Output Data Fall Time 100 ns |
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