Digital pulse compression module

CI F06 Expander and Compressor

Oct 16

CI F06 Expander and Compressor Revision B3

2 / 9

www.rakon.com

Technical description

CI F06 functional block diagram is featured on Fig. 1.

Fig. 1 : CI F06 functional block diagram

Unit description.

The internal low noise system clock is locked on an external clock (derived from the RADAR system clock). For

proper operation, the clock should be a good quality clock, with a low phase noise close to the carrier.

CI F06 unit is provided with FPGA firmware loaded. Functions, and channels specifications (time dispersion,

compressed pulse width, side lobes level…) should be provided by customer; Rakon will customize the FPGA

program to fulfill customer requirements.

CI F06 unit continuously monitors internal power supply and FPGA program integrity. If voltage exceeds nominal

levels, or if FPGA program is corrupted, Unit_OK output is deasserted, and LED is turned off. The Unit_OK output

indicates the GO-NOGO state of the compressor.

Pulse expander channel description.

After each Trigger pulse, a chirp defined by the samples set selected by WFMSel_E is generated, and presented

to the DAC input to be translated into an analog signal. Trigger input have to be synchronized with Clock input.

For better compatibility with old SAW based subsystems, an adjustable additional delay may be inserted.

Expander waveform is selected among 2 possible waveforms, using WFMSel_E input, as presented in Table 1.

Each time WFMSel_E signal changes, the new set of waveform coefficients will be active for the next trigger

pulse.

Table 1 : Expander waveform selection

WFMSel_E

Expander waveform

0

Waveform E0 (TBD)

1

Waveform E1 (TBD)

To

Ba seBa nd

FIR

Filter

Power

Control

Connect

JTA G

Program

FPGA

FPGA

To

F0

Sy stem

Clock

Superv ision

BIT E

Unit_O K

In_ C

Out_C

Power S upply

Wa veform

selection

WF MS el_C

ADC

To

F0

Out_E

DA C

Stored

Wa veforms

Tim ing

Wa veform

selection

WF MS el_E

Trigger

DA C

Clock