ESS Technology, Inc.

SAM0076-051701

3

ES3207 VIDEO CD CC PRODUCT BRIEF

PIN DESCRIPTION

TSD

21

I

Transmit audio data input.

TBCK

22

I

Transmit audio bit clock.

RWS

23

O

Dual-purpose pin. RWS is the receive audio frame sync.

SEL_PLL1

I

Pins SEL_PLL[1:0] select the PLL clock frequency for the DCLK output.

RSTOUT#

24

O

Reset output (active-low).

NC

27:28,65:76

No connect. Do not connect to these pins.

RSD

33

O

Dual-purpose pin. RSD is the receive audio data input.

SEL_PLL0

I

SEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the DCLK out-

put. See the table for pin number 23.

RBCK

37

O

Dual-purpose pin. RBCK is the receive audio bit clock.

SER_IN

I

SER_IN is the serial input DSC mode.

0 = Parallel DSC mode.

1 = Serial DSC mode.

VSSA

41,50:51,56:57,62:63

I

Analog ground.

VREFM

42

I

DAC and ADC minimum reference. Bypass to VCMR with 10

µF in parallel with 0.1 µF.

VREFP

43

I

DAC and ADC maximum reference. Bypass to VCMR with 10

µF in parallel with 0.1 µF.

VCCA

44:45,59:60

I

Analog VCC, 5 V.

AOR

46

O

Right channel output.

AOL

47

O

Left channel output.

MIC2

48

I

Microphone input 2.

MIC1

49

I

Microphone input 1.

VREF

52

I

Internal resistor divider generates Common Mode Reference (CMR) voltage.

Bypass to analog ground with 0.1

µF.

VCM

53

I

ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25 V.

Bypass to analog ground with 47

µF electrolytic in parallel with 0.1 µF.

RSET

54

I

Full scale DAC current adjustment.

COMP

55

I

Compensation pin.

CDAC

58

O

Modulated chrominance output.

YDAC

61

O

Y luminance data bus for screen video port.

VDAC

64

O

Composite video output.

XOUT

71

O

Crystal output.

XIN

74

I

27 MHz crystal input.

PCLK

79

I/O

13.5 MHz pixel clock.

PCLK2X

80

I/O

27 MHz (2 times pixel clock).

HSYNC#

82

O

Horizontal sync (active-low).

VSYNC#

84

O

Vertical sync (active-low).

YUV[7:0]

86:89,92,94,96,98

I

YUV data bus for screen video port.

Name

Number

I/O

Definition

SEL_PLL1

SEL_PLL0

DCLK

0

0

Bypass PLL (input mode)

0

1

27 MHz (output mode)

1

0

32.4 MHz (output mode)

1

1

40.5 MHz (output mode)