L5988D datasheet(13/52 Pages) STMICROELECTRONICS

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L5988D

Functional description

Below follows a brief description of the main blocks:



A voltage pre-regulator supplies the internal circuitry. The external 1.8 V voltage

reference is supplied by this regulator.



A voltage monitor circuit that checks the input and internal voltages



A fully integrated sawtooth oscillator whose frequency is 400 kHz ± 10% when the Fsw

pin is floating. Its frequency can be increased/decreased connecting a proper resistor

to GND or VREF



The internal current limitation circuitry monitors the current flowing in both embedded

switches to guarantee an effective protection even in extreme duty cycle conditions



The over voltage protection (OVP) monitors the feedback voltage. If the voltage of this

pin overcomes the 20% of the internal reference value (600 mV ± 1%) it will force the

conduction of the low side switch until the overshoot is present



A voltage mode amplifier. The inverting input and the output are externally available for

compensation



A pulse width modulator (PWM) comparator and the relative logic to drive the

embedded switches



The soft-start circuit charges an external capacitor with a constant current equal to

20 µA (typ.). The soft-start feature is realized clamping the output of the error amplifier

until the voltage across the capacitor is below 2.7 V



The circuitry acting on the SYNCH pin provides external signal reference to slave

devices when the regulator works as a master or accept the synchronization from an

external reference source



The circuitry related to the UOS multifunction pin is composed of a 3 bit A/D converter

and the decoding logic. It recognizes eight different voltage windows of a VREF voltage

magnitude for selecting additional features.



An inhibit block for stand-by operation



A circuit to realize the thermal protection function

5.1

Multifunction pin

The UOS pin is used to configure the device additional features accordingly to the voltage

bias imposed through VREF voltage partitioning.

The selectable options are:



UVLO level: two pre-defined the under voltage lock out thresholds can be selected to

match the 3.3 V and 5 V or 12 V power bus



SINK capability: this feature is always disabled during the soft-start period to be

compatible with pre-biased output voltages. After the soft-start phase, the synchronous

rectification can be enabled or not depending on the status of the UOS pin. Anyway, in

case an overvoltage is detected, the sink capability is always enabled to bring the FB

back to regulation as fast as possible



OVP management: in case the latched mode is selected and an overvoltage event

recurs, the switching activity will be suspended until VCC is reapplied or the SS/INH pin

is toggled. Otherwise when the overvoltage transient is ended the regulator will work

accordingly to the load request without regulation discontinuity

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