HCF4017B

6/11

TYPICAL APPLICATIONS

DIVIDE

BY

N

COUNTER(N

<

10)

WITH

DECODED OUTPUTS

clock pulse) the S-R flip-flop (constructed from two

NOR gates of the HCF4001B) generates a reset

pulse which clears the HCF4017B to its zero

to clock the next HCF4017B counter section. The

"0" decoded output also goes high at this time.

Coincidence of the clock low and decoded "0"

output high resets the S-R flip-flop to enable the

6, the COUT line will not go high and, therefore,

cannot be used. In this case "0" decoded output

may be used to perform the clocking function for

the next counter.

TEST CIRCUIT