HC123 datasheet(5/6 Pages) NSC

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sistor REXT toward VCC When the voltage across CEXT

equals VREF2 comparator C2 changes state causing the

output latch to reset (Q goes low) while at the same time

disabling comparator C2 This ends the timing cycle with the

monostable in the quiescent state waiting for the next trig-

ger

A valid trigger is also recognized when trigger input B goes

from GND to VCC (while input A is at GND and input clear is

at VCCk) The ’HC123A can also be triggered when clear

goes from GND to VCC (while A is at GND and B is at

VCCo)

It should be noted that in the quiescent state CEXT is fully

charged to VCC causing the current through resistor REXT to

be zero Both comparators are ‘‘off’’ with the total device

current due only to reverse junction leakages An added

feature of the ’HC123A is that the output latch is set via the in-

put trigger without regard to the capacitor voltage Thus prop-

agation delay from trigger to Q is independent of the value

of CEXT REXT or the duty cycle of the input waveform

RETRIGGER OPERATION

The ’HC123A is retriggered if a valid trigger occurs l fol-

lowed by another trigger m before the Q output has re-

turned to the quiescent (zero) state Any retrigger after the

timing node voltage at the RCEXT pin has begun to rise

from VREF1 but has not yet reached VREF2 will cause an

increase in output pulse width T When a valid retrigger is

initiated m the voltage at the RCEXT pin will again drop to

VREF1 before progressing along the RC charging curve

toward VCC The Q output will remain high until time T after

the last valid retrigger

Because the trigger-control circuit flip-flop resets shortly af-

ter CX has discharged to the reference voltage of the lower

reference circuit the minimum retrigger time trr is a function

of internal propagation delays and the discharge time of CX

trr

20 a

187

VCC b 07

565 a (0256 VCC)CX

VCC b 07 2

Another removalretrigger time occurs when a short clear

pulse is used Upon receipt of a clear the one shot must

charge the capacitor up to the upper trip point before the

one shot is ready to receive the next trigger This time is

dependent on the capacitor used and is approximately

trr e 196 a

640

VCC b 07

522 a (03 VCC)CX

(VCC b 07)2

RESET OPERATION

These one shots may be reset during the generation of the

output pulse In the reset mode of operation an input pulse

on clear sets the reset latch and causes the capacitor to be

fast charged to VCC by turning on transistor Q1 n When

the voltage on the capacitor reaches VREF2 the reset latch

will clear and then be ready to accept another pulse If the

clear input is held low any trigger inputs that occur will be

inhibited and the Q and Q outputs of the output latch will

not change Since the Q output is reset when an input low

level is detected on the Clear input the output pulse T can

be made significantly shorter than the minimum pulse width

specification

Typical Output Pulse Width vs

Timing Components

TLF5206 – 7

Typical Distribution of Output

Pulse Width Part to Part

TLF5206 – 8

Typical 1ms Pulse Width

Variation vs Supply

TLF5206 – 9

Minimum REXT vs

Supply Voltage

TLF5206 – 10

Typical 1ms Pulse Width

Variation vs Temperature

TLF5206 – 11

Note

R and C are not subjected to temperature The C is polypropylene

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