ADA4622-2ACPZ-R7 datasheet(24/34 Pages) AD

24 / 34 page

ADA4622-1/ADA4622-2

Data Sheet

Rev. B | Page 24 of 34

THEORY OF OPERATION

SLEW

ENHANCEMENT

CIRCUIT

ED1

+IN x

V–

OUT x

V+

–IN x

ED2

R10

OUTPUT

STAGE

VBIAS

OUT1

OUT2

ED3

ED4

ED5

ED6

IMAGIC

CURRENT

CURRENT MIRROR

Figure 79. Simplified Circuit Diagram

INPUT CHARACTERISTICS

The ADA4622-1/ADA4622-2 input stage consists of N-channel,

JFETs that provide low offset, low noise, and high impedance.

The minimum input common-mode voltage extends from

−0.2 mV below V− to 1 V less than V+. Driving the input

closer to the positive rail causes loss of amplifier bandwidth

and increased common-mode voltage error. Figure 80 shows

the rounding of the output due to the loss of bandwidth. The

input and output are superimposed.

CH1 1.00V CH2 1.00V

M2.00µs

A CH1

3.00V

Figure 80. Bandwidth Limiting due to Headroom Requirements

The ADA4622-1/ADA4622-2 do not exhibit phase reversal for

input voltages up to V+. For input voltages greater than V+, a

10 kΩ resistor in series with the noninverting input prevents

phase reversal at the expense of higher noise (see Figure 81).

CH1 1.00V CH2 1.00V

M2.00µs

A CH1

3.84V

Figure 81. No Phase Reversal

Because the input stage uses N-channel JFETs, the input current

during normal operation is negative. However, the input bias

current changes direction as the input voltage approaches V+

due to internal junctions becoming forward-biased (see Figure 82).

–3

–2

–1

–5

–4

–3

–2

–1

234

COMMON-MODE VOLTAGE (V)

Figure 82. Input Bias Current vs. Common-Mode Voltage with ±5 V Supply

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