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MP45DT02TR-M 数据表(PDF) 7 Page - STMicroelectronics |
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MP45DT02TR-M 数据表(HTML) 7 Page - STMicroelectronics |
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7 / 16 page ![]() MP45DT02-M Acoustic and electrical specifications DocID029435 Rev 1 7/16 2.2 Timing characteristics Table 5: Timing characteristics Parameter Description Min Max Unit fCLK Clock frequency for normal mode 1 3.25 MHz fPD Clock frequency for power-down mode 0.23 MHz TCLK Clock period for normal mode 308 1000 ns TR,EN Data enabled on DATA line, L/R pin = 1 30 (1) ns TR,DIS Data disabled on DATA line, L/R pin = 1 16 (1)(2) ns TL,EN Data enabled on DATA line, L/R pin = 0 30 (1) ns TL,DIS Data disabled on DATA line, L/R pin = 0 16 (1)(2) ns Notes: (1) From design simulations (2)In order to measure the disable time, a 1 kΩ pull-down resistor must be added to the DOUT pin. Figure 2: Timing waveforms |
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