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TLV70235DBVT 数据表(PDF) 16 Page - Texas Instruments |
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TLV70235DBVT 数据表(HTML) 16 Page - Texas Instruments |
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16 / 33 page ![]() COUT VOUT VIN GND PLANE CIN Represents via used for application specific connections IN GND OUT NC EN NC TLV702 SLVSAG6C – SEPTEMBER 2010 – REVISED MARCH 2015 www.ti.com Layout Examples (continued) Figure 29. Layout Example for the DSE Package 10.3 Thermal Consideration Thermal protection disables the output when the junction temperature rises to approximately 165°C, allowing the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. The internal protection circuitry of the TLV702 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TLV702 into thermal shutdown degrades device reliability. 10.4 Package Mounting Solder pad footprint recommendations for the TLV702 are available from the TI website at www.ti.com. The recommended land pattern for the DBV and DSE packages are shown in Figure 28 and Figure 29, respectively. 16 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TLV702 |
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