SiC620, SiC620A

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Vishay Siliconix

S14-2385-Rev. E, 08-Dec-14

13

Document Number: 62922

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Step 5: Signal Routing

1. Route the PWM / ZCD_EN# / DSBL# / THWn signal

traces out of the top left corner next DrMOS pin 1.

2. PWM signal is very important signal, both signal and

return traces need to pay special attention of not letting

this trace cross any power nodes on any layer.

3. It is best to “shield” traces form power switching nodes,

4. GL (pin 27) has been connected with GL pad internally

and does not need to connect externally.

Step 6: Adding Thermal Relief Vias

pads to utilize inner layers for high-current and thermal

dissipation.

2. To achieve better thermal performance, additional vias

vias on this plane.

4. 8 mil drill for pads and 10 mils drill for plane can be the

optional via size. Vias on pad may drain solder during

assembly and cause assembly issue. Please consult

with the assembly house for guideline.

Step 7: Ground Connection

1. It is recommended to make single connection between

layer.

2. It is recommended to make the whole inner 1 layer (next

3. These ground planes provide shielding between noise

source on top layer and signal trace on bottom layer.

plane

V

IN

P

GND

C

GND