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OMAP3530ECBBLPD 数据表(PDF) 71 Page - Texas Instruments

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部件名 OMAP3530ECBBLPD
功能描述  Applications Processors
PDF  265 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBBLPD 数据表(HTML) 71 Page - Texas Instruments

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OMAP3530, OMAP3525
www.ti.com
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
Table 2-3. Ball Characteristics (CUS Pkg.) (continued)
BALL
BALL TOP [2] PIN NAME [3] MODE [4]
TYPE [5]
BALL RESET BALL RESET RESET REL.
POWER [9]
HYS [10]
BUFFER
PULLUP
BOTTOM [1]
STATE [6]
REL. STATE
MODE [8]
STRENG TH
/DOWN TYPE
[7]
(mA) [11]
[12]
A5
sdrc_dqs0
0
IO
L
Z
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
A13
sdrc_dqs1
0
IO
L
Z
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
A8
sdrc_dqs2
0
IO
L
Z
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
A17
sdrc_dqs3
0
IO
L
Z
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
K4
gpmc_a1
0
O
L
L
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_34
4
IO
safe_mode
7
K3
gpmc_a2
0
O
L
L
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_35
4
IO
safe_mode
7
K2
gpmc_a3
0
O
L
L
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_36
4
IO
safe_mode
7
J4
gpmc_a4
0
O
L
L
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_37
4
IO
safe_mode
7
J3
gpmc_a5
0
O
L
L
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_38
4
IO
safe_mode
7
J2
gpmc_a6
0
O
H
H
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_39
4
IO
safe_mode
7
J1
gpmc_a7
0
O
H
H
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_40
4
IO
safe_mode
7
H1
gpmc_a8
0
O
H
H
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_41
4
IO
safe_mode
7
H2
gpmc_a9
0
O
H
H
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
sys_
1
I
ndmareq2
gpio_42
4
IO
safe_mode
7
G2
gpmc_a10
0
O
H
H
7
vdds_ mem
Yes
4
PU/ PD
LVCMOS
sys_
1
I
ndmareq3
gpio_43
4
IO
safe_mode
7
L2
gpmc_d0
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
M1
gpmc_d1
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
M2
gpmc_d2
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
N2
gpmc_d3
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
M3
gpmc_d4
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
P1
gpmc_d5
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
P2
gpmc_d6
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
R1
gpmc_d7
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
R2
gpmc_d8
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_44
4
IO
safe_mode
7
T2
gpmc_d9
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_45
4
IO
safe_mode
7
U1
gpmc_d10
0
IO
H
H
0
vdds_ mem
Yes
4
PU/ PD
LVCMOS
gpio_46
4
IO
safe_mode
7
Copyright © 2008–2013, Texas Instruments Incorporated
TERMINAL DESCRIPTION
71
Submit Documentation Feedback
Product Folder Links: OMAP3530 OMAP3525



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