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OMAP3530ECBC72 数据表(PDF) 59 Page - Texas Instruments

部件名 OMAP3530ECBC72
功能描述  Applications Processors
PDF  265 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBC72 数据表(HTML) 59 Page - Texas Instruments

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OMAP3530, OMAP3525
www.ti.com
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
Table 2-2. Ball Characteristics (CBC Pkg.)(1) (continued)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
i2c2_sccbe
2
O
i2c3_sccbe
3
O
gpio_170
4
IO
safe_mode
7
-
AD15
NA
i2c4_scl
0
IOD
H
H
0
vdds
Yes
3
PU100/
Open Drain
PD100
sys_nvmode
1
O
4
1
safe_mode
7
-
4
W16
NA
i2c4_sda
0
IOD
H
H
0
vdds
Yes
3
PU100/
Open Drain
PD100
sys_nvmode
1
O
4
2
safe_mode
7
-
4
F3
NA
sys_boot0
0
I
Z
Z
0
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_2
4
IO
safe_mode
7
-
D3
NA
sys_boot1
0
I
Z
Z
0
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_3
4
IO
safe_mode
7
-
C3
NA
sys_boot2
0
I
Z
Z
0
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_4
4
IO
safe_mode
7
-
E3
NA
sys_boot3
0
I
Z
Z
0
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_5
4
IO
safe_mode
7
-
E4
NA
sys_boot4
0
I
Z
Z
0
vdds
Yes
4
PU100/
LVCMOS
PD100
mmc2_dir_da
1
O
t2
gpio_6
4
IO
safe_mode
7
-
G3
NA
sys_boot5
0
I
Z
Z
0
vdds
Yes
4
PU100/
LVCMOS
PD100
mmc2_dir_da
1
O
t3
gpio_7
4
IO
safe_mode
7
-
D4
NA
sys_boot6
0
I
Z
Z
0
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_8
4
IO
safe_mode
7
-
AE14
NA
sys_clkout1
0
O
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_10
4
IO
safe_mode
7
-
W11
NA
sys_clkout2
0
O
L
L
7
vdds
Yes
4
(14)
PU100/
LVCMOS
PD100
gpio_186
4
IO
safe_mode
7
-
W15
NA
sys_clkreq
0
IO
0
1
0
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_1
4
IO
safe_mode
7
-
V16
NA
sys_nirq
0
I
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
(14) The capacity load range is [2 pf to 6 pF].
Copyright © 2008–2013, Texas Instruments Incorporated
TERMINAL DESCRIPTION
59
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Product Folder Links: OMAP3530 OMAP3525



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