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OMAP3530ECUS72 数据表(PDF) 48 Page - Texas Instruments

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部件名 OMAP3530ECUS72
功能描述  Applications Processors
PDF  265 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECUS72 数据表(HTML) 48 Page - Texas Instruments

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OMAP3530, OMAP3525
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.)(1) (continued)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
NA
B3
sdrc_d6
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
B4
sdrc_d7
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
A10
sdrc_d8
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
B11
sdrc_d9
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
A11
sdrc_d10
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
B12
sdrc_d11
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
A16
sdrc_d12
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
A17
sdrc_d13
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
B17
sdrc_d14
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
B18
sdrc_d15
0
IO
L
Z
0
vdds
Yes
4
(2)
PU100/
LVCMOS
PD100
NA
B7
sdrc_d16
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
A5
sdrc_d17
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
B6
sdrc_d18
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
A6
sdrc_d19
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
A8
sdrc_d20
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
B9
sdrc_d21
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
A9
sdrc_d22
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
B10
sdrc_d23
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
C21
sdrc_d24
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
D20
sdrc_d25
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
B19
sdrc_d26
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
C20
sdrc_d27
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
D21
sdrc_d28
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
E20
sdrc_d29
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
E21
sdrc_d30
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
G21
sdrc_d31
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
H1
sdrc_dm0
0
O
0
0
0
vdds
No
4
(3)
NA
LVCMOS
NA
A14
sdrc_dm1
0
O
0
0
0
vdds
No
4
(3)
NA
LVCMOS
NA
A4
sdrc_dm2
0
O
0
0
0
vdds
No
4
(3)
NA
LVCMOS
NA
A18
sdrc_dm3
0
O
0
0
0
vdds
No
4
(3)
NA
LVCMOS
NA
C2
sdrc_dqs0
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
B15
sdrc_dqs1
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
B8
sdrc_dqs2
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
NA
A19
sdrc_dqs3
0
IO
L
Z
0
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
(3)
The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the
selected mode.
48
TERMINAL DESCRIPTION
Copyright © 2008–2013, Texas Instruments Incorporated
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Product Folder Links: OMAP3530 OMAP3525



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