STMPE16M31PX datasheet(22/75 Pages) STMICROELECTRONICS

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System controller

STMPE16M31PX

22/75

Doc ID 17058 Rev 2

SYSCON-2

Sensor and PWM clock divider

Address:

0x04

Type:

R/W

Reset:

0xFE

Description:

Sensor and PWM clock divider. The SYSCON-2 register controls the sensor and

PWM clock speed, and the clock gating of various functional modules.

This bit will always read '0'. as the I2C transaction to read this bit will wake up the

device from hibernate mode.

543

210

SCLK_DIV

PCLK_DIV

GPIO_CLK

PWM_CLK

CS_CLK

[7:5] SCLK_DIV: Sensor clock divider.

000, 001: RESERVED

010 : 32 (to be used only if load capacitance is < 30 pF)

011: 64

100: 128

101: 256

110: 512

111: 1024

Sensor clock is 2 MHz / ( PRBS_Factor * SCLK_DIV[2:0] )

PRBS factor is a pseudo-random sequence of number, ranging from 1-8. This is used to reduce

the effect of surrounding EMI on the sensor. Average of this factor is approximately 2.5

Effective sampling rate is 2 MHz/ (2.5*SCLK_DIV[2:0]).

Maximum total sampling rate : 2MHz/(2.5*64) = 12.5 kHz

Minimum total sampling rate : 2 MHz/(2.5*1024) = 780 Hz

If N channel is active, the per-channel sampling rate is “total sampling rate / N”.

Maximum channel sampling rate = 12.5 kHz/24 = 521 Hz

[4:3] PCLK_DIV: PWM clock divider

00 for 16 kHz

01 for 32 kHz

10 for 64 kHz

11 for 128 kHz

Obsolete

Product(s)

- Obsolete

Product(s)

STMPE16M31PX 数据表(PDF) 22 Page - STMicroelectronics

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