PC8477B datasheet(13/54 Pages) NSC

13 / 54 page

30 Register Description (Continued)

381 DIRPC-AT Mode

DESC

DSKCHG

RESET

COND

Disk Changed

Active high status of DSKCHG

disk interface input independent of INVERT

value

D6 – D0

Undefined

TRI-STATE Used by hard disk con-

troller status register

382 DIRPS2 Mode

DESC

DSKCHG

DRATE1 DRATE0

HIGH

DEN

RESET

NA NA NA NA

COND

Disk Changed

Active high status of DSKCHG

disk interface input independent of INVERT

value

D6 – D3

Reserved

Always 1

D2 – D1

Data Rate Select 10

These bits indicate the

status of the DRATE1 – 0 bits programmed

through the DSRCCR

High Density

This bit is low when the 1 Mbs

or 500 kbs data rate is chosen and high when

the 300 kbs or 250 kbs data rate is chosen

This bit is independent of the IDENT or INVERT

value

383 DIRModel 30 Mode

D6 D5 D4

DESC

DSKCHG 0

0 DMAEN NOPRE DRATE1 DRATE0

RESET

COND

Disk Changed

Active low status of DSKCHG

disk interface input independent of INVERT

value

D6 – D4

Reserved

Always 0

DMA Enable

Active high status of the DMAEN

bit in the DOR

No Precompensation

Active high status of the

NOPRE bit in the CCR

D1 – D0

Data Rate Select 10

These bits indicate the

status of the DRATE1 – 0 bits programmed

through the DSRCCR

39 CONFIGURATION CONTROL REGISTER (CCR)

Write

Only

This is the write only data rate register commonly used in

PC-AT applications This register is not affected by a soft-

ware reset and is set to 250 kbs after a hardware reset

The data rate of the floppy controller is determined by the

last write to either the CCR or DSR

391 CCRPC-AT and PS2 Modes

DESC

DRATE1 DRATE0

RESET

NA NA NA NA NA NA

COND

D7 – D2

Reserved

Should be set to 0

D1 – D0

Data Rate Select 10

These bits determine the

data rate of the floppy controller See Table 3-6

for the appropriate values

392 CCRModel 30 Mode

D7 D6 D5 D4 D3

DESC

NOPRE DRATE1 DRATE0

RESET

NA NA NA NA NA

COND

D7 – D3

Reserved

Should be set to 0

No Precompensation

This bit can be set by

software but it has no functionality It can be

read by bit D2 of the DIR when in the Model 30

D1 – D0

Data Rate Select 10

These bits determine the

data rate of the floppy controller See Table 3-6

for the appropriate values

310 RESULT PHASE STATUS REGISTERS

The Result Phase of a command contains bytes that hold

status information The format of these bytes are described

below Do not confuse these status bytes with the Main

Status Register which is a read only register that is always

valid The Result Phase status registers are read from the

Data Register (FIFO) only during the Result Phase of certain

commands (see Section 41 Command Set Summary) The

status of each register bit is indicated when the bit is a 1

3101 Status Register 0 (ST0)

DESC

HDS

DS1

DS0

RESET

COND

D7 – D6

Interrupt Code

00 e Normal Termination of Command

01 e Abnormal Termination of Command Exe-

cution of command was started but was

not successfully completed

10 e Invalid Command Issued Command is-

sued was not recognized as a valid com-

mand

11 e Internal drive ready status changed state

during the drive polling mode Only occurs

after a hardware or software reset

Seek End

Seek Relative Seek or Recalibrate

command completed by the controller (Used

during a Sense Interrupt command)

Equipment Check

After a Recalibrate com-

mand Track 0 signal failed to occur (Used dur-

ing Sense Interrupt command)

Not Used Always 0

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