IPN2M50T-H datasheet(18/25 Pages) STMICROELECTRONICS

18 / 25 page

Application circuit example

STIPN2M50T-H

18/25

DocID028651 Rev 5

5.1

Guidelines



Input signals HIN, LIN are active high logic. A 37

5 kΩ (typ.) pull-down resistor is built-

in for each input. To prevent input signal oscillations, the wiring of each input should

be as short as possible and the use of RC filters (R1, C1) on each input signal is

suggested. The filters should be with a time constant of about 100 ns and placed as

close as possible to the IPM input pins.



The use of a bypass capacitor CVCC (aluminum or tantalum) can help to reduce the

transient circuit demand on the power supply. Besides, to reduce high frequency

switching noise distributed on the power lines, a decoupling capacitor C2 (100 to 220

nF, with low ESR and low ESL) should be placed as close as possible to Vcc pin and in

parallel whit the bypass capacitor.



The use of RC filter (RSF, CSF) for circuit malfunction protection is recommended.

The time constant (RSF x CSF) should be set to 1 μs and the filter must be placed as

close as possible to the CIN pin.



The

̅̅̅̅ is an input/output pin (open-drain type if used as output). A built-in thermistor

NTC is internally connected between the

̅̅̅̅ pin and GND. The voltage VSD-GND

decreases as the temperature increases, due to the pull-up resistor RSD. In order to

keep the voltage always higher than the high level logic threshold, the pull-up resistor

is suggested to be set to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supply,

respectively. The CSD capacitor of the filter on

̅̅̅̅ should be fixed no higher than 3.3

nF in order to assure a

̅̅̅̅ activation time Ƭ

<= 500 ns and the filter should be placed

as close as possible to the

̅̅̅̅ pin.



The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR and low

ESL), in parallel with each Cboot, filters high frequency disturbance. Both Cboot and C3

(if present) should be placed as close as possible to the U, V, W and Vboot pins.

Bootstrap negative electrodes should be connected to U, V, W terminals directly and

separated from the main output wires.



To prevent the overvoltage on Vcc pin, a Zener diode (Dz1) can be used. Similarly on

the Vboot pin, a Zener diode (Dz2) can be placed in parallel with each Cboot.



The use of the decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in

parallel with the electrolytic capacitor Cvdc is useful to prevent surge destruction. Both

capacitors C4 and Cvdc should be placed as close as possible to the IPM (C4 has

priority over Cvdc).



By integrating an application-specific type HVIC inside the module, direct coupling to

the MCU terminals without an optocoupler is possible.



Use low inductance shunt resistors for phase leg current sensing.



In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND

should be as short as possible.



The connection of SGN_GND to PWR_GND to one point only (close to the shunt

resistor terminal) can help to reduce the impact of power ground fluctuation.

These guidelines ensure the specifications of the device for application designs. For further

details, please refer to the relevant application note.

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