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2.2.6

Plug and Play Protocol

The following protocol is based on the Plug and Play

ISA Specification 1.0a. It should be applied on power-

up, if during reset BADDR1 = 0 and BADDR0 = 1. It is

not applicable otherwise. For any other reset values

of BADDR0,1, the hardware does not respond.

This protocol is used to determine the addresses of

the INDEX and DATA registers. When the protocol is

applied, the CPU interrupts should be disabled.

Upon power up, an initiation key must be written to

one of the following I/O ports: 279h, 3BDh or 3F0h.

The initiation key consists of a predefined series of

write operations. All of the write operations in the se-

ries must be to the same port. These ports are write

only. The ports are chosen so as to avoid conflicts in

the installed base of ISA functions. (These ports serve

as read-only registers in legacy devices.) The write

sequence is decoded by the Chip.

If the proper series of I/O writes is detected, the con-

figuration of the Chip base address (address of the In-

dex register) follows. The base address of the Chip is

configured by two additional I/O writes to the chosen

I/O port (the same I/O port to which the initiation key

was written). The data in the first write holds the eight

high address bits of the Chip base address. The data

in the second write holds the eight low address bits of

the Chip base address. Once these two I/O writes are

accomplished, the INDEX and DATA registers are ac-

cessible and the Chip is configurable.

Since this protocol is based on the Plug and Play ISA

Specification 1.0a, software should conclude this pro-

tocol with a sequence of two write cycles of 0x00 to

the chosen I/O port. Once the Plug and Play protocol

is concluded, it can not be applied again until a hard-

ware reset is asserted. CPU interrupts can be en-

abled at this point. The addresses of the INDEX and

DATA registers are still reconfigurable, via the SBAL

and SBAH configuration registers, as explained in the

Section “Relocating the INDEX and DATA Register

Pair” on page 40.

The hardware check of the initiation key is implement-

ed as a linear feedback shift register (LFSR). See

“The Linear Feedback Shift Register (LFSR)” on page

40. Software generates the LFSR sequence and

writes it to one of the three I/O ports defined above as

a sequence of 8-bit write cycles (all writes are to the

same I/O port). Hardware compares the byte of write

data with the value in the shift register at each write.

When the data does not match, the hardware resets

to the initial value of the LFSR. Software should reset

the LFSR to its initial value using a sequence of two

write cycles of 0x00 to the chosen port (one of the

three I/O ports) before the initiation key is sent.

Figure 1 shows the flowchart of the Plug and Play pro-

tocol.

FIGURE 1. Plug and Play Protocol Flowchart

Reset

Wait for Key

Is this

the first value

of the key?

Save the address

Wait for the

next value of

the key

Is this

the next value

in the key?

Is this

the last value

in the key?

SBAH

update mode

Update SBAH with

the data

SBAL

update mode

Update SBAL with

the data

INDEX and DATA

registers are

accessible

Reset signal inactive

I/O Write to 279h, 3F0h or 3BDh

I/O write to the saved address

Any

End

Any other I/O

transaction

Any other I/O

transaction

Any other I/O

transaction

Yes

Initial value of the key = 0x6A,

Whenever the Chip is in the Wait for Key state,

Last value in the key = 0x00.

the LFSR is initialized with 0x6A.

other

I/O

transaction

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