PC97338 datasheet(48/221 Pages) NSC

48 / 221 page

www.national.com

FIGURE 5. PTR Register Bitmap

Bit 0 - Power Down

Setting this bit causes all enabled functions to be

powered down.

Bits 3 and 2 of PCR can affect this function.

0 - Functions not powered down.

1 - Setting this bit causes all enabled functions to

be powered down. All register data is retained

when the clocks are stopped. The FDC, SCCs

and parallel port are affected by this bit when

the relevant PMC register bits and SCF0 reg-

ister bits are set.

Bit 1 - Reserved

This bit is reserved.

Bit 2 - Reserved

This bit is reserved and must be set to 0.

Bit 3 - Select IRQ5 or IRQ7

In Plug and Play mode, this bit is ignored.

In Legacy mode, setting this bit associates the par-

allel port with IRQ7 when the address for the par-

allel port is 378 - 37Fh (LPT2). This bit is ignored

when the parallel port address is 3BC - 3BEh

(LPT1) or 278 - 27Fh (LPT3).

0 - LPT2 not associated with IRQ7

1 - LPT2 associated with IRQ7

Bit 4 - SCC1 Test Mode

Setting this bit puts SCC1 into a test mode, which

causes its BAUDOUT clock to be present on its

SOUT1 pin if the bit 7 of the Line Control Register

(LCR) is set to 1.

0 - No test mode

1 - Test mode.

Bit 5 - Reserved

This bit is reserved.

Bit 6 - Lock Configuration

Setting this bit to 1 prevents all further write ac-

cesses to the Configuration Registers. Once it is

set by software it can only be cleared by a hard-

ware reset. After the initial hardware reset it is 0.

0 - Configuration Registers accessible. (Default)

1 - Configuration Registers locked.

Bit 7 - Select Extended or Compatible Parallel Port

When not in EPP or ECP modes, this bit controls

SPP (Standard Parallel Port) mode (Compatible or

Extended mode), thus controlling Pulse/Level in-

terrupt:

In EPP mode this bit should be 0. In ECP mode,

this bit is ignored.

0 - Compatible mode, pulse interrupt.

1 - Extended mode, level interrupt.

2.3.5

Function Control Register (FCR),

Index 03h

This register determines several pin options. It selects

Data Rate output or automatic media sense input sig-

nals.

For Enhanced Parallel Port it enables the ZWS op-

tions and pin.

On reset, bits 7-1 of FCR are cleared to 0.

FIGURE 6. FCR Register Bitmap

Bit 0 - TDR Mode Select

This bit selects TDR mode when bit 2 of ASC is ze-

ro.

This bit is ignored when bit 2 of ASC is 1 (see bit 2

of ASC for complete TDR mode selection). This bit

is initialized to 1 during reset, thus selecting AT

Compatible TDR.

0 - TDR is in Automatic Media Sense Mode. Bits

7-5 of TDR are valid.

1 - TDR is in AT Compatible Mode. Bits 7-2 of

TDR are in TRI-STATE during read. (Default)

543

Reset

Required

Power and Test

Index 02h

Power Down

Reserved

Select IRQ5 or IRQ7

SCC1 Test Mode

Reserved

Lock Configuration

Select Extended or Compatible Parallel Port

543

Reset

Required

Function Control

Index 03h

TDR Mode Select

Select MSEN0 or DRATE0

Select ZWS or CS1

Reserved

Parallel Port Float Control

Clock Multiplier Test Bit

Zero Wait State Enable

Reserved

PC97338 数据表(PDF) 48 Page - National Semiconductor (TI)

PC97338 数据表(HTML) 48 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

PC97338 数据表(PDF) 48 Page - National Semiconductor (TI)

PC97338 数据表(HTML) 48 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载