SN54ABT853, SN74ABT853

8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198G − FEBRUARY 1991 − REVISED OCTOBER 2010

3

POST OFFICE BOX 655303

logic diagram (positive logic)

PARITY

ERR

CLR

B1−B8

A1−A8

LE

OEA

OEB

EN

EN

8x

8x

MUX

1

1

G1

1

1

2k

P

8

9

8

8

8

8

Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

2−9

14

1

13

11

23−16

15

10

ERROR-FLAG FUNCTION TABLE

INPUTS

INTERNAL

TO DEVICE

OUTPUT

PRESTATE

OUTPUT

ERR

FUNCTION

CLR

LE

POINT P

ERR

FUNCTION

L

L

L

X

L

Pass

L

L

H

X

H

Pass

L

X

L

H

L

X

LL

Sample

H

L

H

HH

Sample

L

H

X

X

H

Clear

H

H

X

L

L

Store

H

H

X

H

H

Store