Application information

HVLED001A

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DocID029000 Rev 2

7.2.2

Feedback input

The FB pin is intended to be connected to the compensation network for the primary side

control (PSR) loop of the output voltage (see Section 7.2.4) as well as to be connected

directly to the collector of the optocoupler that provides the galvanic insulation to the

secondary side regulation control loop.

In case of constant output voltage applications, the PSR loop can be used to regulate the

output voltage saving the secondary side error amplifier.

The FB voltage is also used as an input parameter for the burst mode operation described in

Section 7.2.5.

The pin embeds a protection to prevent from the operation with a failed optocoupler.

7.2.3

Zero current detection

The zero level detection is performed by a trigger logic that, once armed (if a ZCD voltage is

higher than VZCD,arm after Tblank,min starting from GD turn-off instant), is sensitive to

falling edges. The advanced ZCD logic is able to discriminate between the normal

operation, output short-circuit or startup condition.

An internal blanking time prevents any triggering signal to activate the MOSFETs at the very

beginning of the off-time, where spurious resonances could be present. As a result, the first

falling edge occurring after the blanking time turns on the MOSFET.

To ensure a proper operation, the transformer has to be designed to guarantee that the

inductor's demagnetization time is longer than TBLANK (at VTOFF > VTOFF,fix) when the

The TOFF pin is intended to select the blanking time duration. If the pin is left unconnected

a fixed blanking time is provided.

The TBLANK value depends on the TOFF voltage (Figure 9).

An internal starter provides the triggering signal whenever a valid arming signal is not

detected.

The ZCD pin embeds a negative clamp to limit the negative-going current.