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L4984D

Overvoltage protection (OVP)

6

Overvoltage protection (OVP)

Normally, the voltage control loop keeps the output voltage Vout of the PFC pre-regulator

close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A

pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a

separate resistor divider (R3 high, R4 low, see Figure 30). This divider is selected so that

the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually

larger than the maximum Vout that can be expected.

Figure 30. Output voltage setting, OVP and FFD functions: internal block diagram

Note:

Select: R3 = 8.8 M; then: R4 = 8.8 M ·2.5/(434-2.5) = 51 k.

When this function is triggered, the gate drive activity is immediately stopped until the

voltage on the pin PFC_OK drops below 2.4 V. Notice that R1, R2, R3 and R4 can be

selected without any constraints. The unique criterion is that both dividers must sink a

current from the output bus which needs to be significantly higher than the bias current of

both pins INV and PFC_OK (< 1

μA).

AM13246v1

Frequency

compensation

2.5 V

+

-

0.23 V

0.27 V

-

+

INV

Disable

OVP

Error Amplifier

COMP

2.5 V

2.4 V

+

-

1.66 V

L_OVP

6

1

2

-

+

PFC_OK

Vout

R1a

R1b

R2

R3a

R3b

R4

R3

R1

L4984D