TNETV2665FIBZWT4 datasheet(95/249 Pages) TI1

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TMS320C6424

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SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

Table 3-18. PINMUX1 Register Description (continued)

Bit

Field Name

Description

Pins Controlled

Host Block*:

See list of 27 pins in HOSTBK bit field

description

PCI Data Block:

AD26

AD28

AD30

GPIO Block:

AD0/GP[0]

PCI Enable.

AD1/GP[1]

AD2/GP[2]

The PINMUX1.PCIEN reflects the state of the PCIEN pin. PINMUX1.PCIEN is AD4/GP[3]

read only and cannot be modified by software. For proper device

operation, the user must hold the desired setting at the PCIEN pin

EMIFA Sub-Block 0*:

throughout device operation.

EM_A[13]/AD25/GP[51]

EM_A[14]/AD27/GP[50]

PCIEN = 0: No PCI supported. Internal pullup/pulldown (IPU/IPD) on these pins

EM_A[15]/AD29/GP[49]

are enabled.

EM_A[16]/PGNT/GP[48]

EM_A[17]/AD31/GP[47]

For PCI multiplexed pins in the GPIO Block, when PCIEN = 0, the pins function

EM_A[18]/PRST/GP[46]

as GPIO (GP[3:0]).

EM_A[19]/PREQ/GP[45]

PCIEN

For PCI multiplexed pins in the Host Block, refer to PINMUX1.HOSTBK field for

EM_A[20]/PINTA/GP[44]

the actual pin functions.

For PCI multiplexed pins in the EMIFA Block, refer to the PINMUX0.AEM field

EMIFA Sub-Block 3*:

for the actual pin functions.

EM_A[12]/PCBE3/GP[89]

For PCI pins in the PCI Data Block, when PCIEN = 0, the pins have no function

EM_A[11]/AD24/GP[90]

and should be left unconnected.

EM_A[10]/AD23/GP[91]

EM_A[9]/PIDSEL/GP[92]

PCIEN = 1: PCI supported. Internal pullup/pulldown (IPU/IPD) on all PCI pins

EM_A[8]/AD21/GP[93]

are disabled.

EM_A[7]/AD22/GP[94]

EM_A[6]/AD20/GP[95]

All pins function as PCI pins.

EM_A[5]/AD19/GP[96]

Applicable only for PINMUX0.AEM = 000b or 101b.

*The pin mux for the EMIFA Sub-Block 0,

EMIFA Sub-Block 3, and Host Block pins are

controlled by a combination of PCIEN and other

PINMUX0/1 fields, including HOSTBK and

AEM. See Section 3.7.3.13.2, EMIFA Block

Pin-By-Pin Multiplexing Summary, for the full

set of valid configurations of EMIFA Block pins.

For the full set of valid configurations of Host

Block pins, see Section 3.7.3.3, Host Block

Muxing.

Device Configurations

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