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TNETV2665FIBZWT7 数据表(PDF) 207 Page - Texas Instruments |
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TNETV2665FIBZWT7 数据表(HTML) 207 Page - Texas Instruments |
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207 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 Table 6-54. Switching Characteristics Over Recommended Operating Conditions for McASP(1) (2) (see Figure 6-32 and Figure 6-33)(3) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. PARAMETER UNIT MIN MAX 9 tc(AHCKRX) Cycle time, AHCLKR/X 25 ns AH - 10 tw(AHCKRX) Pulse duration, AHCLKR/X high or low ns 2.5 11 tc(CKRX) Cycle time, ACLKR/X(4) ACLKR/X int 25 ns 12 tw(CKRX) Pulse duration, ACLKR/X high or low ACLKR/X int A - 2.5 ns ACLKR/X int -2.25 5.5 ns ACLKR/X 0 12.5 ns 13 td(CKRX-FRX) Delay time, ACLKR/X transmit edge to AFSX/R output valid ext input ACLKR/X 0 14 ns ext output ACLKX int -2.25 5.5 ns ACLKX 0 12.5 ns 14 td(CKX-AXRV) Delay time, ACLKX transmit edge to AXR output valid ext input ACLKX 0 14 ns ext output ACLKR/X int -4.5 8 ns Disable time, AXR high impedance following last data bit from 15 tdis(CKRX-AXRHZ) ACLKR/X transmit edge ACLKR/X ext -4.5 12.5 ns (1) A = (ACLKR/X period)/2 in ns. For example, when ACLKR/X period is 25 ns, use A = 12.5 ns. (2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns. (3) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 (4) There is a clock ratio requirement between the system infrastructure clock, SYSCLK3, and the McASP0 bit clocks, ACLKR/ACLKX. For proper device operation, the ACLKR/ACLKX frequency must be no faster than ½ of SYSCLK3 frequency. Copyright © 2007–2009, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 207 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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