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TNETV2665FIBZWT7 数据表(PDF) 4 Page - Texas Instruments |
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TNETV2665FIBZWT7 数据表(HTML) 4 Page - Texas Instruments |
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4 / 249 page  JTAGInterface SystemControl PLLs/ClockGenerator Input Clock(s) Power/Sleep Controller PinMultiplexing DSP C64x+™ DSP CPU 32KB L1Pgm 128KBL2RAM 80KB L1Data SwitchedCentralResource(SCR) Peripherals EDMA I2C UART SerialInterfaces DDR2 MemCtlr (32b) AsyncEMIF/ NAND/ (16b) Program/DataStorage Watchdog Timer PWM System General- Purpose Timer VLYNQ EMAC With MDIO Connectivity HPI McASP McBSP OSC BootROM GPIO PCI (33MHz) TMS320C6424 SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 www.ti.com 1.3 Functional Block Diagram Figure 1-1 shows the functional block diagram of the C6424 device. Figure 1-1. TMS320C6424 Functional Block Diagram 4 TMS320C6424 Fixed-Point Digital Signal Processor Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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