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TNETV2665FIBZWT7 数据表(PDF) 216 Page - Texas Instruments |
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TNETV2665FIBZWT7 数据表(HTML) 216 Page - Texas Instruments |
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216 / 249 page  MRCLK 2 3 1 MTCLK 2 3 1 TMS320C6424 SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 www.ti.com 6.15.3 EMAC Electrical Data/Timing (MII and RMII) 6.15.3.1 EMAC MII Electrical Data/Timing Table 6-59. Timing Requirements for MRCLK - MII Operation (see Figure 6-34) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. UNIT 10 Mbps 100 Mbps MIN MAX MIN MAX 1 tc(MRCLK) Cycle time, MRCLK(1) 400 40 ns 2 tw(MRCLKH) Pulse duration, MRCLK high 140 14 ns 3 tw(MRCLKL) Pulse duration, MRCLK low 140 14 ns (1) There is a clock ratio requirement between the system infrastructure clock, SYSCLK3, and the EMAC receive/transmit input clocks, MRCLK and MTCLK. For proper device operation, the SYSCLK3 frequency must be faster than 12.5 MHz. Figure 6-34. MRCLK Timing (EMAC - Receive) [MII Operation] Table 6-60. Timing Requirements for MTCLK - MII Operation (see Figure 6-34) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. UNIT 10 Mbps 100 Mbps MIN MAX MIN MAX 1 tc(MTCLK) Cycle time, MTCLK(1) 400 40 ns 2 tw(MTCLKH) Pulse duration, MTCLK high 140 14 ns 3 tw(MTCLKL) Pulse duration, MTCLK low 140 14 ns (1) There is a clock ratio requirement between the system infrastructure clock, SYSCLK3, and the EMAC receive/transmit input clocks, MRCLK and MTCLK. For proper device operation, the SYSCLK3 frequency must be faster than 12.5 MHz. Figure 6-35. MTCLK Timing (EMAC - Transmit) [MII Operation] Table 6-61. Timing Requirements for EMAC MII Receive 10/100 Mbit/s(1) (see Figure 6-36) -7/-6/-5/-4 -L/-Q6/-Q5/- NO. UNIT Q4 MIN MAX 1 tsu(MRXD-MRCLKH) Setup time, receive selected signals valid before MRCLK high 8 ns 2 th(MRCLKH-MRXD) Hold time, receive selected signals valid after MRCLK high 8 ns (1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER. 216 Peripheral Information and Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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