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TNETV2665ZWT4 数据表(PDF) 168 Page - Texas Instruments |
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TNETV2665ZWT4 数据表(HTML) 168 Page - Texas Instruments |
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168 / 249 page  TMS320C6424 SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 www.ti.com 6.8 Interrupts The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for each of the 12 CPU interrupts is user programmable and is listed in Table 6-21. Also, the interrupt controller controls the generation of the CPU exception and emulation interrupts. The NMI input to the C64x+ DSP interrupt controller is not connected internally, therefore the NMI interrupt is not available. Table 6-22 summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP interrupt control, see the TMS320C64x+ DSP Megamodule Reference Guide (literature number SPRU871). Table 6-21. C6424 DSP System Event Mapping DSP DSP SYSTEM SYSTEM ACRONYM SOURCE ACRONYM SOURCE EVENT EVENT NUMBER NUMBER 0 EVT0 C64x+ Int Ctl 0 64 GPIO0 GPIO 1 EVT1 C64x+ Int Ctl 1 65 GPIO1 GPIO 2 EVT2 C64x+ Int Ctl 2 66 GPIO2 GPIO 3 EVT3 C64x+ Int Ctl 3 67 GPIO3 GPIO 4 TINTL0 Timer 0 – TINT12 68 GPIO4 GPIO 5 TINTH0 Timer 0 – TINT34 69 GPIO5 GPIO 6 TINTL1 Timer 1 – TINT12 70 GPIO6 GPIO 7 TINTH1 Timer 1 – TINT34 71 GPIO7 GPIO 8 WDINT Timer 2 – TINT12 72 GPIOBNK0 GPIO 9 EMU_DTDMA C64x+ EMC 73 GPIOBNK1 GPIO 10 Reserved 74 GPIOBNK2 GPIO 11 EMU_RTDXRX C64x+ RTDX 75 GPIOBNK3 GPIO 12 EMU_RTDXTX C64x+ RTDX 76 GPIOBNK4 GPIO 13 IDMAINT0 C64x+ EMC 0 77 GPIOBNK5 GPIO 14 IDMAINT1 C64x+ EMC 1 78 GPIOBNK6 GPIO 15 Reserved 79 Reserved 16 Reserved 80 PWM0 PWM0 17 Reserved 81 PWM1 PWM1 18 Reserved 82 PWM2 PWM2 19 Reserved 83 IICINT0 I2C 20 Reserved 84 UARTINT0 UART0 21 Reserved 85 UARTINT1 UART1 22 Reserved 86 Reserved 23 Reserved 87 Reserved 24 Reserved 88 Reserved 25 Reserved 89 Reserved 26 Reserved 90 Reserved 27 Reserved 91 Reserved 28 Reserved 92 Reserved 29 Reserved 93 Reserved 30 Reserved 94 Reserved 31 Reserved 95 Reserved Reserved INTERR C64x+ Interrupt Controller Dropped CPU 32 96 Interrupt Event 33 Reserved 97 EMC_IDMAERR C64x+ EMC Invalid IDMA Parameters 34 EDMA3CC_GINT EDMACC Global Interrupt 98 Reserved 35 EDMA3CC_INT0 EDMACC Interrupt Region 0 99 Reserved 36 EDMA3CC_INT1 EDMACC Interrupt Region 1 100 Reserved 37 EDMA3CC_ERRINT EDMA CC Error 101 Reserved 38 EDMA3TC_ERRINT0 EDMA TC0 Error 102 Reserved 39 EDMA3TC_ERRINT1 EDMA TC1 Error 103 Reserved 40 EDMA3TC_ERRINT2 EDMA TC2 Error 104 Reserved 41 PSCINT PSC ALLINT 105 Reserved 168 Peripheral Information and Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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