TNETV2665ZWT4 datasheet(8/249 Pages) TI1

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TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

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Table 2-1. Characteristics of the C6424 Processor (continued)

HARDWARE FEATURES

C6424

1.43 (-7)

1.67 (-6/-Q6)

CVDD = 1.2 V

2 (-5/-Q5)

2.5 (-4/-Q4)

Cycle Time(1)

1.79 (-7)

2.22 (-6)

CVDD = 1.05 V

2.5 (-5/-Q5/-L)

2.8 (-4)

1.2 V

(-7/-6/-5/-4/-Q6/-Q5/-Q4)

Core (V)

Voltage(1)

1.05 V

(-7/-6/-5/-4/-L/-Q5)

I/O (V)

1.8 V, 3.3 V

MXI/CLKIN frequency multiplier

PLL Options

x1 (Bypass), x14 to x32

(15-30 MHz reference)

16 x 16 mm, 0.8 mm pitch

361-Pin BGA (ZWT)

BGA Package(s)

23 x 23 mm, 1.0 mm pitch

376-Pin BGA (ZDU)

Process Technology

µm

0.09 µm

Product Preview (PP), Advance Information (AI),

Product Status(2)

or Production Data (PD)

(2)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

2.2

C64x+ Megamodule

The C64x+ Megamodule (Figure 2-1) consists of the following components:

•

TMS320C64x+ CPU

•

Internal memory controllers:

–

Level-1 program memory controller (L1P controller)

–

Level-1 data memory controller (L1D controller)

–

Level-2 unified memory controller (L2 controller)

–

External memory controller (EMC)

–

Internal direct memory access (IDMA) controller

•

Internal peripherals

–

Interrupt controller (INTC)

–

Power-down controller (PDC)

The following C64x+ Megamodule standard features are not supported on the C6424 device:

•

Memory Protection

•

Power-down of the internal memories (L1P, L1D, and L2)

For more detailed information on the C64x+ Megamodule, see the TMS320C64x+ DSP Megamodule

Reference Guide (literature number SPRU871).

Device Overview

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Product Folder Link(s): TMS320C6424

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