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TNETV2665ZWT4 数据表(PDF) 134 Page - Texas Instruments

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部件名 TNETV2665ZWT4
功能描述  Fixed-Point Digital Signal Processor
PDF  249 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETV2665ZWT4 数据表(HTML) 134 Page - Texas Instruments

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DSP
SYSCLK1
SYSCLK3
SCR
EDMA
DDR2PHY
DDR2VTP
DDR2MemCtlr
PLLDIV2(/10)
PLLDIV1(/2)
BPDIV
PLL Controller2
PLL Controller1
PLLDIV2(/3)
PLLDIV3(/6)
PLLDIV1(/1)
SYSCLK2
UARTs(x2)
I2C
Timers(x3)
PWMs(x3)
EMAC
EMIFA
VLYNQ
HPI
McASP0
McBSP0
GPIO
McBSP1
PCI
MXI/CLKIN
(15-30MHz)
OSCDIV1(/1)
OBSCLK
(CLKOUT0Pin)
AUXCLK
TMS320C6424
SPRS347D – MARCH 2007 – REVISED DECEMBER 2009
www.ti.com
The CLKDIV1:CLKDIV3:CLKDIV6 ratio must be strictly followed by programming the PLL Controller 1
(PLLC1) PLLDIV1, PLLDIV2, and PLLDIV3 registers appropriately (see Table 6-3).
Table 6-3. PLLC1 Programming for CLKDIV1, CLKDIV3, CLKDIV6 Domains
CLKDIV1 DOMAIN
CLKDIV3 DOMAIN
CLKDIV6 DOMAIN
(SYSCLK1)
(SYSCLK2)
(SYSCLK3)
PLL1
PLL1
PLL1
PLLDIV1.RATIO
PLLDIV2.RATIO
PLLDIV3.RATIO
Divide-Down
Divide-Down
Divide-Down
DIV1
/1
0
/3
2
/6
5
DIV2
/2
1
/6
5
/12
11
DIV3
/3
2
/9
8
/18
17
Figure 6-4. PLL1 and PLL2 Clock Domain Block Diagram
For further detail on PLL1 and PLL2, see the structure block diagrams Figure 6-5 and Figure 6-6,
respectively.
134
Peripheral Information and Electrical Specifications
Copyright © 2007–2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320C6424



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