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TNETV2666FIBZWT 数据表(PDF) 163 Page - Texas Instruments |
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TNETV2666FIBZWT 数据表(HTML) 163 Page - Texas Instruments |
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163 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 Table 6-15. PLLC1 Clock Frequency Ranges CLOCK SIGNAL NAME MIN MAX UNIT MXI/CLKIN(1) 15 30 MHz -7 devices 300 700 MHz PLLOUT CVDD = 1.2 V -6/-5/-4/-Q6/-Q5/-Q4 devices 300 600 MHz -7 devices 300 520 MHz PLLOUT CVDD = 1.05 V -6/-5/-4/-L/-Q5 devices 300 520 MHz -7 devices 700 MHz -6/-Q6 devices 600 MHz SYSCLK1(2) (CLKDIV1 Domain), CVDD = 1.2 V -5/-Q5 devices 500 MHz -4/-Q4 devices 400 MHz -7 devices 520 MHz -6 devices 450 MHz SYSCLK1(2) (CLKDIV1 Domain), CVDD = 1.05 V -5/-Q5/-L devices 400 MHz -4 devices 350 MHz (1) MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2). (2) Applies to "tape and reel" part number counterparts as well. For more information, see Section 2.7 , Device and Development-Support Tool Nomenclature. Table 6-16. PLLC2 Clock Frequency Ranges CLOCK SIGNAL NAME MIN MAX UNIT MXI/CLKIN(1) 15 30 MHz At 1.2-V CVDD 300 900 MHz PLLOUT At 1.05-V CVDD 300 666 MHz PLL2_SYSCLK1 (to DDR2 PHY) 333 MHz (1) MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2). Both PLL1 and PLL2 have stabilization, lock, and reset timing requirements that must be followed. The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after the PLL is powered up (after PLLCTL.PLLPWRDN bit goes through a 1-to-0 transition). The PLL should not be operated until this stabilization time has expired. This stabilization step must be applied after these resets—a Power-on Reset, a Warm Reset, or a Max Reset, as the PLLCTL.PLLPWRDN bit resets to a "1". For the PLL stabilization time value, see Table 6-17. The PLL reset time is the amount of wait time needed for the PLL to properly reset (writing PLLRST = 0) before bringing the PLL out of reset (writing PLLRST = 1). For the PLL reset time value, see Table 6-17. The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). For the PLL lock time value, see Table 6-17. Table 6-17. PLL1 and PLL2 Stabilization, Lock, and Reset Times PLL STABILIZATION/LOCK/RESET MIN TYP MAX UNIT TIME PLL Stabilization Time 150 μs PLL Lock Time 2000C(1) ns PLL Reset Time 128C(1) ns (1) C = CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 25 MHz, use C = 40 ns. Copyright © 2007–2009, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 163 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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