PD interface

PM8801

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DocID018560 Rev 2

4.4

Undervoltage lockout

After classification is completed, the PSE raises the voltage to provide the Powered Device

with the negotiated power. During the transition from low to operating voltage, the internal

UVLO is released and the hot-swap MOSFET is activated, initiating the inrush sequence.

PM8801 implements the UVLO mechanism by setting 2 internal thresholds on the voltage

normal operating conditions.

No additional external components are required to comply with the IEEE requirements. The

thermal protection alarm overrides the gate driving of the MOS, immediately switching off

the MOS itself in case of device overheating. The hot-swap is bypassed also in auxiliary

source topology, supplying directely the PWM section of the PM8801 and bypassing the hot-

swap MOSFET.

4.5

Inrush and DC current limiting

Once the detection and classification phases have been succesfully completed, the PSE

raises the voltage across the Ethernet cable. When the voltage difference between VIN and

and the DC/DC input capacitance is charged in a controlled manner.

During the inrush phase the current is limited to 140 mA.

When the RTN voltage falls below 1.5 V, an internal signal (PGOOD in Figure 3 ) is asserted

to activate the DC/DC section.

This feature is active only when working from an input voltage with a "frontal" connection,

that must use the hot-swap MOSFET; this voltage could be from the PoE interface or from

an external auxiliary adapter connected before the internal hot-swap MOSFET. If the

auxiliary source is connected after the hot-swap MOSFET, it will be opened and this feature

is disabled, allowing the converter to work with a low-voltage auxiliary source. The PGOOD

comparator includes hysteresis to allow the PM8801 to operate near the current limit point

without inadvertently disabling it. The MOSFET voltage must increase to 12 V before

PGOOD is deasserted. This feature will also allow withstanding positive line transients of up

to 12 V without stopping DC/DC normal operations as shown in Figure 9. The line transient

is managed by the PWM section, adjusting its operating parameters accordingly without

shutting down the output voltage. The input current during the transient is controlled by the

hot-swap MOSFET at the DC current limit.

After PGOOD assertion, a comparator on the gate of the hot-swap MOSFET controls the

transition between the 140 mA to the 640mA DC current limit, with a 2 V threshold. The

comparator is needed to ensure that the charge of the DC/DC input capacitor is completed,

avoiding current spikes on the last portion of the charge.