SPV1050 datasheet(14/36 Pages) STMICROELECTRONICS

14 / 36 page

Functional description

SPV1050

14/36

DocID025569 Rev 4

Figure 3. Battery management section

Before the first startup the pass transistor is open, so that the leakage from the battery is

lower than 1 nA. The pass transistor will be closed once the voltage on the STORE pin will

rise such that the EOC threshold VEOC is triggered. If the battery is full, and until

VSTORE > VEOC - EOCHYS, the DC-DC converter will stop switching to avoid battery

overcharge.

On the contrary, in order to avoid the overdischarge of the battery, the pass transistor will be

opened once the voltage on the STORE pin will decrease down to UVP threshold VUVP.

These functions are simply implemented by the control of two voltage thresholds, VUVP and

VEOC, which can be regulated by a resistor partitioning (R4, R5, R6) between STORE, UVP

and EOC pins.

The scaled voltages on the UVP and EOC pins will be compared with the internal bandgap

voltage reference VBG set at 1.23 V.

The design rules to setup the R4, R5 and R6 are the following:

Equation 1

VBG = VUVP • (R5 + R6) / (R4 + R5 + R6)

Equation 2

VBG = VEOC • R6 / (R4 + R5 + R6)

In order to minimize the leakage due to the output resistor partitioning it has to be typically:

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