STBC02 datasheet(22/39 Pages) STMICROELECTRONICS

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Functional pin description

STBC02

22/39

DocID029261 Rev 2

6.12

CEN

Internal CC/CV charger block enable pin. A low logic level on this pin disables the internal

CC/CV charger block. Transitioning CEN from high to low and then back to high, allows the

CC/CV charger block to be restarted if it was stopped due to one of the following

conditions:



Charging timeout (pre-charge, fast charge)



Battery voltage below VPRE after the fast charge has already started



End-of-charge

CEN has no effect if the charging cycle has been stopped by a battery overcharge

condition.

If the CC/CV charger stops the charging cycle due to an out of range battery temperature,

a low logic level on the CEN pin disables the CC/CV charger and resets the charging

timeout timers. If CEN is set high, the CC/CV charger restarts normal operations, assuming

that no fault condition is detected. CEN is interna

lly pulled up to LDO via a 500 kΩ resistor

and must be either left floating or tied to LDO when the STBC02 is powered for the first

time. Should the auto-recharge function be enabled, the CC/CV charger restarts

automatically charging the battery if VBAT goes below 3.9 V; a deglitch time delay has been

added to prevent unwanted charging cycle restarts.

6.13

RESET_NOW (RESET_CLEAR), nRESET, RST_PENDING

The device features reset/watchdog circuits meant to be used in conjunction with the

external application processor or with other embedded devices; it provides a reset signal or

a watchdog expiration information. The reset signal and the watchdog timer expiration have

no impact on the STBC02 operations.

6.13.1

Smart reset section control pins

The smart reset circuit is active only when a valid VIN is present (VUVLO < VIN < VINOVP). The

STBC02 features a 150 ms deglitch time, starting from the valid VIN detection, and it is

meant to avoid false triggering due to signal bounces. After VIN is considered to be valid

and the deglitch time has expired, the RST_PENDING signal goes to a high logic level. An

nRESET signal is generated automatically after a 4000 ms delay, starting from the end of

the deglitch time, or anytime earlier if a RESET_NOW signal is applied. This is a sole event

and no other nRESET signal is generated as long as VIN is disconnected and reconnected

again. The RST_PENDING signal remains at a high logic level until when one of the two

prior conditions is met. For more details refer to the following timing diagram.

Figure 19: Smart reset timing diagram

The nRESET pull-up resistor must be connected to LDO pin or to a higher voltage.

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