STODD01

Application information

Doc ID 17789 Rev 2

23/31

Equation 7

where

Δ I

Equation 8

The use of ceramic capacitors with voltage ratings in the range higher than 1.5 times the

maximum input or output voltage is recommended.

9.5

Layout considerations

Due to the high switching frequency and peak current, the layout is an important design step

for all switching power supplies. Important parameters (efficiency, output voltage ripple,

switching noise immunity, etc.) can be affected if the PCB layout is not designed with close

attention to the following DC-DC general layout rules, such as:

●

Short, wide traces must be implemented for mains current and for power ground paths.

The input capacitor must be placed as close as possible to the IC pins as well as the

inductor and output capacitor.

●

The feedback pin (FB) connection to the external resistor divider is a high impedance

node, so interference can be minimized by placing the routing of the feedback node as

far as possible from the high current paths. To reduce pick up noise the resistor divider

must be placed very close to the device.

●

A common ground node minimizes ground noise.

●

The exposed pad of the package must be connected to the common ground node.

Moreover, the exposed pad ground connection must be properly designed in order to

facilitate the heat dissipation from the exposed pad to the ground layer using PCB vias, as

shown in the recommended PCB layout of Figure 34, 35, and 36.

⎥

⎦

⎤

⎢

⎣

⎡

×

×

+

×

Δ

=

SW

OUT

L

RIPPLE

_

OUT

F

C

8

1

ESR

I

V

(

)

⎥

⎦

⎤

⎢

⎣

⎡

×

×

−

+

×

=

SW

OUT

OUT

IN

OUT

OUT

RIPPLE

_

OUT

F

C

V

V

V

ESR

I

V