TDA7564

14/20

face, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).

Data Validity

As shown by fig. 22, the data on the SDA line must be stable during the high period of the clock. The HIGH and

LOW state of the data line can only change when the clock signal on the SCL line is LOW.

Start and Stop Conditions

As shown by fig. 23 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop

condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.

Byte Format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.

The MSB is transferred first.

Acknowledge

The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 24).

The receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so

that the SDAline is stable LOW during this clock pulse.

* Transmitter

= master (

µP) when it writes an address to the TDA7564

= slave (TDA7564) when the

µP reads a data byte from TDA7564

** Receiver

= slave (TDA7564) when the

µP writes an address to the TDA7564

= master (

µP) when it reads a data byte from TDA7564

SDA

SCL

DATA LINE

STABLE, DATA

VALID

CHANGE

DATA

ALLOWED

D99AU1031

SCL

SDA

START

STOP

D99AU1032

SCL

1

MSB

23789

SDA

START

ACKNOWLEDGMENT

FROM RECEIVER

D99AU1033