DM8147SCIS0 datasheet(21/377 Pages) TI1

21 / 377 page

TMS320DM8148, TMS320DM8147

www.ti.com

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

2.7

Media Controller Overview

The Media Controller has the responsibility of managing the HDVPSS, HDVICP2, and ISS modules.

For more details on the Media Controller, see the Media Controller Subsystem section of the Chip Level

Resources chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual

(Literature Number: SPRUGZ8).

2.8

HDVICP2 Overview

The HDVICP2 is a Video Encoder/Decoder hardware accelerator supporting a range of encode, decode,

and transcode operations for most major video codec standards. The main video Codec standards

supported in hardware are MPEG1/2/4 ASP/SP, H.264 BL/MP/HP, VC-1 SP/MP/AP, RV9/10, AVS-1.0,

and ON2 VP6.2/VP7.

The HDVICP2 hardware accelerator is composed of the following elements:

•

Motion estimation acceleration engine

•

Loop filter acceleration engine

•

Sequencer, including its memories and an interrupt controller

•

Intra-prediction estimation engine

•

Calculation engine

•

Motion compensation engine

•

Entropy coder/decoder

•

Video Direct Memory Access (DMA)

•

Synchronization boxes

•

Shared L2 controller

•

Local interconnect

For more details on the HDVICP2, see the HD Video Coprocessor SubSystem section of the Chip Level

Resources chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual

(Literature Number: SPRUGZ8).

Device Overview

Submit Documentation Feedback

Product Folder Links: TMS320DM8148 TMS320DM8147

DM8147SCIS0 数据表(PDF) 21 Page - Texas Instruments

DM8147SCIS0 数据表(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载