TNETV2685FIBZUT11 datasheet(6/191 Pages) TI1

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TMS320DM647

TMS320DM648

SPRS372H – MAY 2007 – REVISED APRIL 2012

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Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history highlights the technical changes made to the SPRS372G device-specific

data manual to make it an SPRS372H revision. Applicable updates to the TMS320DM64x Digital Media

Processors device family , specifically relating to the TMS320DM647, TMS320DM648 devices which are

now in the production data (PD) stage of development, have been incorporated.

DM647/DM648 Revision History

SEE

ADDITIONS, DELETIONS, MODIFICATIONS

External Memory Interfaces (EMIFs):

Section 1

•

Deleted the footnote reference (1) from "512M-Byte Address Space (1.8-V I/O)" subbullet

•

Deleted associated footnote [devices are PD; SR1.0 was TMX]

Section 1.1

Added separate Applications section (new format structure)

Terminal Functions, Power Pins:

Table 2-4

•

Added "or left unconnected" to the VCCMON (L19) pin DESCRIPTION column [For the Advisory, see the

Device-Specific Silicon Errata.]

Figure 6-5

Corrected CLKDIR to VLYNQ to show 0 is VLYNQ, external

PLL1 Controller Device-Specific Information

•

Added "[When SYSCLK4 is used as the EMIF input clock source, the actual clock goes through a

Section 6.4.1

divider and the frequency would be SYSCLK4 divide-by-2 (see Figure 6-5, PLL Input Clock).]" to the

SYSCLK4 is used as the EMIFA AECLKOUT bullet [Cleared Doc Feedback]

Timing Requirements for Asynchronous Memory Cycles for EMIFA Module:

Table 6-44

•

Changed 3ns to 0ns for th(AOEH-EDV)

Figure 6-21

Updated to show times 3 and 4 are referred to rising edge AAOE/ASOE.

Table 6-49

Changed 5.4ns to 4.2ns for tw(VKIH) and tw(VKIL).

Section 7.2

Deleted duplicated Orderable Addendum table

Contents

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