TNETV2685FIBZUTA9 datasheet(86/191 Pages) TI1

86 / 191 page

TMS320DM647

TMS320DM648

SPRS372H – MAY 2007 – REVISED APRIL 2012

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After the reset sequence, the boot sequence begins. Since the boot and configuration pins are not

latched with a max reset, the previous values (as shown in the BOOTCFG register) are used to

select the bootmode. For more details on the boot sequence, see the Using the

TMS320DM647/DM648 Bootloader Application Report (literature number SPRAAJ1). After the boot

sequence, follow the software initialization sequence.

6.7.4

System Reset

A system reset maintains memory contents and does not reset the clock logic or the test and emulation

circuitry. The device configuration pins are also not re-latched and the state of the peripherals

(enabled/disabled) is also not affected. A system reset is initiated by the PRST pin of PCI peripheral.

During a system reset, the following happens:

1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to

propagate through the system. Internal system clocks are not affected.

2. After the internal reset signal has propagated, the PLL controllers pause and restart their system

clocks for about 10 cycles of their system reference clocks, but retain their configuration. The PLLs

also remain locked.

3. The boot sequence is started after the system clocks are restarted. Since the configuration pins

(including the BOOTMODE[3:0] pins) are not latched with a system reset, the previous values, as

shown in the BOOTCFG register, are used to select the boot mode.

6.7.5

Peripheral Local Reset

The user can configure the local reset and clock state of a peripheral through programming the PSC.

Table 6-2 identifies the LPSC numbers and the peripherals capable of being locally reset by the PSC. For

detailed

information

the

programming

these

peripherals

the

PSC,

see

the

TMS320DM647/TMS320DM648 DSP Subsystem Reference Guide (literature number SPRUEU6).

6.7.6

Reset Priority

If any of the above reset sources occur simultaneously, the PLLCTRL processes only the highest priority

reset request. The reset request priorities are as follows (high to low):

•

Power-on Reset

•

Maximum Reset

•

Warm Reset

•

System Reset

Peripheral Information and Electrical Specifications

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