TNETV2685FIDZUT9 datasheet(2/191 Pages) TI1

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TMS320DM647

TMS320DM648

SPRS372H – MAY 2007 – REVISED APRIL 2012

www.ti.com

• VLYNQ™ Interface (FPGA Interface)

(Multiplexed With Other Device Functions)

• On-Chip ROM Bootloader

• Package:

• Individual Power-Saving Modes

– 529-pin nFBGA (ZUT suffix)

• Flexible PLL Clock Generators

– 19x19 mm 0.8 mm pitch BGA

• IEEE-1149.1 (JTAG™) Boundary-Scan-

– 0.09-

μm/6-Level Cu Metal Process (CMOS)

Compatible

• 3.3-V and 1.8-V I/O, 1.2-V Internal (-720, -800, -

• 32 General-Purpose I/O (GPIO) Pins

900, -1100)

1.1

Applications

•

Digital Video Recording

1.2

Trademarks

TMS320C64x+, C64x, C64x+, VelociTI, VelociTI.2, VLYNQ, TMS320C6000, C6000, TI, and TMS320 are

trademarks of Texas Instruments.

I2C Bus is a registered trademark of Koninklijke Philips Electronics N.V.

Windows is a registered trademark of Microsoft Corporation in the United States and/or other countries.

All trademarks are the property of their respective owners.

1.3

Description

The TMS320C64x+™ DSPs (including the TMS320DM647/TMS320DM648 devices) are the highest-

performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM647, DM648

devices are based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-

word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice

for digital media applications. The C64x+™ devices are upward code-compatible from previous devices

that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an

expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and

C64x+ CPU, respectively.

With performance of up to 8800 million instructions per second (MIPS) at a clock rate of 1.1 GHz, the

C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses

the operational flexibility of high-speed controllers and the numerical capability of array processors. The

C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly

independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The

eight functional units include instructions to accelerate the performance in video and imaging applications.

The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for up to 4400 million MACs

per second (MMACS), or eight 8-bit MACs per cycle for up tp 8800 MMACS. For more details on the

C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature

number SPRU732).

The devices also have application-specific hardware logic, on-chip memory, and additional on-chip

peripherals similar to the other C6000 DSP platform devices. The core uses a two-level cache-based

architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data

cache (L1D) is a 256K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 4M-

bit (DM648) or 2M-bit (DM647) memory space that is shared between program and data space. L2

memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes five configurable 16-bit video port peripherals (VP0, VP1, VP2, VP3, and

VP4). These video port peripherals provide a glueless interface to common video decoder and encoder

devices. The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-

BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M), a VCXO interpolated control port (VIC); a 1000

Mbps Ethernet Switch Subsystem with a management data input/output (MDIO) module and two SGMII

Features

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Product Folder Link(s): TMS320DM647 TMS320DM648

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