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STSPIN32F0 数据表(PDF) 21 Page - STMicroelectronics |
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STSPIN32F0 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 40 page  DocID029806 Rev 2 21/40 STSPIN32F0 Device description 40 If the failure event occurs on the SW pin and the IOVC threshold is reached the regulator is latched off. To restart the DC/DC regulator a power-down and power-up cycle of device supply voltage (VM) is mandatory. If the failure event occurs on the regulator output (VDDA pin) and the voltage goes below the UVLO threshold (VDDOff), the regulator restarts with a new soft-start sequence until the OC condition is removed. In this case the current in the coil is limited by ISW.peak. The DC/DC regulator embeds a thermal protection as described in Section 6.1.2. Figure 7. DC/DC buck regulator topology Figure 8. Soft-start timing |
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