A5974D datasheet(39/46 Pages) STMICROELECTRONICS

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A5974D

Application information

8.10

Synchronization example

See Section 5.3 on page 10 for details.

Figure 30. Synchronization example

8.11

Compensation network with MLCC at the output

The A5974D standard compensation network (please refer to Figure 1 on page 1 and

Section 7 on page 16) introduces a single zero and a low frequency pole in the system

bandwidth, so a high ESR output capacitor must be selected to compensate the 180 degree

phase shift given by the LC double pole.

The selection of the output capacitor has to guarantee that the zero introduced by this

component is inside the designed system bandwidth and close to the frequency of the

double pole introduced by the LC filter. A general rule for the selection of this compound for

the system stability is provided in Equation 51.

Equation 51

MLCCs (multiple layer ceramic capacitor) with values in the range of 10 µF - 22 µF and

rated voltages in the range of 10 V - 25 V are available today at relatively low cost from

many manufacturers.

These capacitors have very low ESR values (a few m

) and thus are occasionally used for

the output filter in order to reduce the voltage ripple and the overall size of the application.

However, the zero given by the output capacitor falls outside the designed bandwidth and so

the system becomes unstable with the standard compensation network.

Figure 31 shows the type III compensation network stabilizing the system with ceramic

capacitors at the output (the optimum components value depends on the application). This

configuration introduces two zeros and a low frequency pole in the designed bandwidth, so

guarantees a proper phase margin.

fZ ESR

 ESR C

OUT





------------------------------------------------

bandwidth



fLC f



Z ESR

10 fLC





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