VIPER53DIP datasheet(17/24 Pages) STMICROELECTRONICS

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VIPer53DIP / VIPer53SP

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introducing a zero and ensuring a correct phase

margin. This configuration is illustrated in figure 18

for the schematic and figure 19 for the error

amplifier transfer function for a typical set of values

for CCOMP and RCOMP. Note that a capacitor of

10 nF (minimum value: 8 nF) should always be

connected to the COMP pin to insure a correct

stability of the internal error amplifier.

The

complete

converter

open

loop

transfer

function can be built from both power cell and error

amplifier transfer functions. A theoretical example

can be seen in figure 20 for a discontinuous mode

flyback loaded by a simple resistor, regulated from

primary side (no optocoupler, the internal error

amplifier is fully used for regulation). A typical

schematic corresponding to this situation can be

seen on figure 14.

The

transfer

function

of the

power

cell

represented as G(s) in figure 20. It exhibits a pole

which depends on the output load and on the

output capacitor value. As the load of a converter

may change, two curves are shown for two

different values of output resistance value, RL1 and

RL2. A zero at higher frequency values then

appears, due to the output capacitor ESR. Note

that the overall transfer function doesn’t depend on

the input voltage, thanks to the current mode

control.

The error amplifier has a fixed behavior, similar to

the one shown in figure 19. Its bandwidth is limited,

in order to avoid injection of high frequency noise

Figure 19: Typical Transfer Functions

Frequency (Hz)

100

10k

100k

Gain (dB)

-10

Rcomp=4.7k

Ccomp=470nF

Frequency (Hz)

Phase (°)

100

10k

100k

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

Rcomp=4.7k

Ccomp=470nF

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