VIPER53 datasheet(15/24 Pages) STMICROELECTRONICS

15 / 24 page

VIPer53DIP / VIPer53SP

15/24

actually an equivalent number of switching pulses

per

second,

rather

than

fixed

switching

frequency, as the device is working in burst mode.

As long as the power remains below PRST the

output of the regulation loop remains stuck at

VCOMPsd and the converter works in burst mode.

Its “density” increases (i.e. the number of missing

cycles decreases) as the power approaches PRST

and resumes finally normal operation at point 1.

The hysteresis cannot be seen on the switching

frequency, but the COMP pin voltage which

passes brutally at that power level from point 3 to

point 1.

The power points value PRST and PSTBY are

defined by the following formulas:

Where Ip(VCOMPbl) is the peak Power MOSFET

current corresponding to a compensation voltage

of VCOMPbl (1V), that is to say about 250 mA. Note

that the power point PSTBY where the converter is

going into burst mode doesn’t depend on the input

voltage.

The standby frequency FSWstb y is given by:

The ratio between the nominal switching frequency

and the standby one can be as high as 4,

depending on the Lp value and input voltage.

HIGH VOLTAGE START-UP CURRENT

SOURCE

An integrated high voltage current source provides

a bias current from the DRAIN pin during the start-

up phase. This current is partially absorbed by

internal control circuits in standby mode with

reduced consumption and also supplies the

external capacitor connected to the VDD pin. As

soon as the voltage on this pin reaches the high

voltage threshold VDDon of the UVLO logic, the

device turns into active mode and starts switching.

The start-up current generator is switched off, and

the converter should normally provide the needed

current on the VDD pin through the auxiliary

winding of the transformer, as shown on figure 14

or 15.

The external capacitor CVDD on the VDD pin must

be sized according to the time needed by the

converter to start-up, when the device starts

switching. This time tss depends on many

parameters, among which transformer design,

output

capacitors,

soft

start

feature

and

compensation network implemented on the COMP

pin and possible secondary feedback circuit. The

following formula can be used for defining the

minimum capacitor needed:

Figure 17 shows a typical start-up event. VDD

starts from 0 V with a charging current IDDch1 at

about 9 mA. When about VDDoff is reached, the

Figure 16: Standby Mode Implementation

VCOMP

VCOMPsd

VCOMPbl

VCOMPoff

600ns

350ns

FSW

FSWnom

FSWstby

PSTBY

PRST

Minimum

ton

turn on

RST

--- F

SWnom

()

------

⋅⋅

⋅

STBY

--- F

SW nom

COMP bl

() Lp

⋅⋅

⋅

SWs tby

STBY

RST

-------------- F

SWnom

⋅

VDD

DD1

tss

⋅

DDhyst

-----------------------

Figure 17: Startup Waveforms

IDD

IDD1

tss

IDDch2

IDDch1

VDDsd

VDDst

VDDreg

VDD

tsu

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