Pin settings

L7987

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DocID025589 Rev 3

2.2

Pin description

Table 1. Pin description

Number

Pin

Description

1

VBIAS

Auxiliary input that can be used to supply part of the analog circuitry to increase the efficiency

at light load. Typically connected to the regulated output voltage or to an external voltage rail

higher than 3 V. Connect to the signal GND if not used or bypass with a 1

F ceramic capacitor

if supplied by the output voltage or by an auxiliary rail.

2

VIN

DC input voltage

3

VIN

DC input voltage

4VCC

Filtered DC input voltage to the internal circuitry. Bypass to the signal GND by a 1

F ceramic

capacitor.

5

EN

Active high enable pin. Connect to the VCC pin if not used.

6SS

An internal current generator (5 µA typ.) charges the external capacitor to implement the soft-

start.

7

SYNCH Master / slave synchronization

8

COMP Output of the error amplifier. The designed compensation network is connected at this pin.

9

FB

Inverting input of the error amplifier.

10

FSW

A pull-down resistor to GND selects the switching frequency.

11

ILIM

A pull-down resistor to GND selects the peak current limitation.

12

PGOOD

The PGOOD open collector output is driven low when the output voltage, sensed on the FB

pin, is out of regulation.

13

LX

Switching node

14

LX

Switching node

15

BOOT

Connect an external capacitor (100 nF typ.) between BOOT and LX pins. The gate charge

required to drive the internal n-DMOS is recovered by an internal regulator during the off-time

16

GND

Signal GND

-

E.P.

Exposed pad must be connected to signal GND.