LDF

Application information

DocID025502 Rev 2

11/33

6

Application information

6.1

External capacitors

The LDF voltage regulator requires external ceramic capacitors to assure the control loop

stability. These capacitors must be selected to meet the requirements of minimum

capacitance and equivalent series resistance (see Figure 25: "Stability plane ADJ (COUT,

ESR)" and Figure 26: "Stability plane 3.3 V (COUT, ESR)". Input/output capacitors should be

located as closer as possible to the relative pins.

6.1.1

Input capacitor

An input capacitor, whose minimum value is 1 μF, must not be located farther than 0.5"

from the input pin of the device and returned to a clean analog ground.

6.1.2

Output capacitor

Ceramic capacitors could be used on the output, provided that they must meet the

minimum amount of capacitance and E.S.R. (equivalent series resistance) value required.

2.2 μF is suggested as minimum capacitance to guarantee the stability of the regulator.

Anyway, other COUT values can be used according to the Figure 25: "Stability plane ADJ

(COUT, ESR)" and Figure 26: "Stability plane 3.3 V (COUT, ESR)" showing the allowable ESR

range as a function of the output capacitance. The output capacitor must maintain its ESR

in the stable region over the full operating temperature range to assure stability. Besides,

capacitor tolerance and temperature variation must be taken into account to assure the

minimum amount of capacitance.

6.2

Output voltage setting for ADJ version

In the adjustable version, the output voltage can be set from 0.8 V up to the input voltage

minus the voltage drop across the pass transistor (dropout voltage), by connecting a

resistor divider between the ADJ pin and the output, thus allowing remote voltage sensing.

The resistor divider could be selected by the following equation:

⁄ )

It is recommended to use resistors with values in the range of 10 kΩ to 100 kΩ. Lower

values can also be suitable, but current consumption increases.

6.3

Enable pin operation

This pin can be used to turn OFF the regulator when it is pulled down, so to drastically

reduce the current consumption. When the enable feature is not used, this pin must be tied

the signal source, used to drive the EN pin, must be able to swing above and below the

floating because it is not internally pulled down/up.

6.4

Power Good

The LDF features an open drain PG pin to sequence either external supplies or loads and

high when the output is within the power-good tolerance window. Typical values for this

resistor range from 10 kΩ to 100 kΩ.