数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

UM1018 数据表(PDF) 13 Page - STMicroelectronics

部件名 UM1018
功能描述  STM32L152-EVAL evaluation board
PDF  42 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

UM1018 数据表(HTML) 13 Page - STMicroelectronics

Back Button UM1018 Datasheet HTML 9Page - STMicroelectronics UM1018 Datasheet HTML 10Page - STMicroelectronics UM1018 Datasheet HTML 11Page - STMicroelectronics UM1018 Datasheet HTML 12Page - STMicroelectronics UM1018 Datasheet HTML 13Page - STMicroelectronics UM1018 Datasheet HTML 14Page - STMicroelectronics UM1018 Datasheet HTML 15Page - STMicroelectronics UM1018 Datasheet HTML 16Page - STMicroelectronics UM1018 Datasheet HTML 17Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 42 page
background image
UM01018
Hardware and layout
Doc ID 18141 Rev 2
13/42
2.13
Comparator
Three I/Os are used to implement a comparator feature as shown in Figure 3.
●
Comparator non-inverting input PB4 connected to LDR (R34).
●
Comparator inverting input PB3 connected to potentiometer (RV3) used as variable
threshold input for comparison to luminosity measured on LDR.
●
Comparator non-inverting input PB5 connected to potentiometer (RV3) used as
analogue voltage input for comparison with internal voltage reference (for instance
Band gap) in order to test analogue Wakeup feature of the MCU.
Figure 3.
STM32L152-EVAL comparator features
Jumper JP17 allows 3 different usages of the potentiometer as shown in Table 10.
Table 10.
Comparator and potentiometer related jumpers
Jumper
Description
Setting
JP17
Potentiometer RV3 is connected to ADC input PB12. Used as ADC input when JP17 is set
as shown (default setting).
Potentiometer RV3 used as LDR variable threshold. Input is connected to comparator
inverting input GPCOMP_IN- (PB3) when JP17 is set as shown.
Potentiometer RV3 is connected to non-inverting input GPCOMP_IN+(PB5).
The comparator inverting input can be connected to ¼ band gap, ½ band gap, band gap or
DAC internally to test MCU wakeup possibility when an external voltage reaches a
programmable threshold when JP17 is set as shown.
JP10
PB4 is connected to JTAG connector CN9 (TRST) when JP10 is set as shown (default
setting).
PB4 is connected to LDR when JP10 is set as shown.
PB12
PB3
PB5
PB12
PB3
PB5
PB12
PB3
PB5
3
2
1
3
2
1



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com