the falling edge of CE are latched in. In

Table 3, the last input

bit prior to to the CE falling edge is the LSB of the ADPCM

data word.

Note that the serial input data is referenced to the falling

edge of CE while the serial output data is referenced to the

rising edge of CE.

Table 4 shows the transfer order of the ADPCM output data.

In the case where there are more ASCK clocks than the AD-

PCM data, the ADPCM output will recirculate.

For example, if the 32 kbps mode is selected, and eight low

pulses of ASCK exist within the CE high pulse, the following

ADPCM encoded data D3-D2-D1-D0-D3-D2-D1-D0 will ap-

pear at the TSO output (

Table 5).

TABLE 3. Transfer Order of ADPCM Input Data (RSI). The Last Bit Prior[to] the Falling Edge of CE is the LSB of the

ADPCM Data

QSEL1

QSEL0

Mode

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0

0

32 kbps

x

D3

D2

D1

D0

0

1

24 kbps

x

D2

D1

D0

x

1

0

16 kbps

x

D1

D0

x

x

1

1

40 kbps

D4

D3

D2

D1

D0

(MSB)

(LSB)

Note 1: x = Don’t Care state

TABLE 4. Transfer Order of ADPCM Output Data (TSO) with 4 ASCK Rising Edgesile CE is High (the First Bit is the

MSB Data Bit following the Rising Edge of CE)

QSEL1

QSEL0

Mode

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0

0

32 kbps

D3

D2

D1

D0

D3

0

1

24 kbps

D2

D1

D0

x

D2

1

0

16 kbps

D1

D0

x

x

D1

1

1

40 kbps

D4

D3

D2

D1

D0

(MSB)

(LSB)

Note 2: x = unknown (but defined) state

TABLE 5. Transfer Order of ADPCM Output Data (TSO)th 7 Rising Edges (7 Low Pulses) while CE is High

QSEL1

QSEL0

Mode

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0

0

32 kbps

D3

D2

D1

D0

D3

D2

D1

D0

0

1

24 kbps

D2

D1

D0

x

D2

D1

D0

x

1

0

16 kbps

D1

D0

x

x

D1

D0

x

x

1

1

40 kbps

D4

D3

D2

D1

D0

D4

D3

D2

Note 3: x = unknown (but defined) state

SINGLE-CHANNEL INITIALIZATION AND

ALL-CHANNEL RESET

The TP11368 ADPCM processor can be initialized on a

per-channel basis via the use of INIT or on an all-channel ba-

sis via the use of RSTB. In both cases, the internal ADPCM

variables are initialized to the default values as suggested by

the ITU G.726 recommendation.

An individual channel can be initialized to the desired con-

figuration by setting the corresponding data variables PCM1,

EN, QSEL(0,1) and by asserting the INIT pin high. The con-

figuration data and INIT signal are strobed at the falling edge

of CE. For an initialization cycle, the period of CE must be 45

master clock (CLK) cycles. The transcoder is then ready to

process the next channel.

The active low RSTB signal is used for a “warm” reset as

well as for facilitating device testing. The initialization of the

internal memory takes 726 CLK cycles after the RSTB goes

inactive (logic “1”). The first transition of CE is allowed six

CLK cycles after RSTB goes inactive. It is recommended

that CE be kept low during the initialization phase.The rec-

ommended values for ASCK and PSCK during initialization

are logic “1”, and that for TSI and RSI logic “0”. Any data (TSI

and RSI) applied during the initialization phase will be lost,

however, they won’t affect the proper initialization process.

The minimum low time of RSTB is 2 CLK cycles.

The chip resumes operation on the first negative edge of CE

after the completion of the initialization.

POWER-ON-RESET

The on-chip Power-On-Reset macro is activated when exter-

nal power is first applied to the device. It has the same func-

tion as the external RSTB pin which initializes all channels to

the default values defined in the ITU Recommendation

G.726. At power up, the outputs TSO and RSO are in

TRI-STATE mode. This “cold” reset process is asynchronous

and takes approximately 2000 CLK cycles for the initializa-

tion.

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