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ST72561J4-Auto 数据表(PDF) 83 Page - STMicroelectronics |
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ST72561J4-Auto 数据表(HTML) 83 Page - STMicroelectronics |
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83 / 324 page ![]() ST72561-Auto Window watchdog (WWDG) Doc ID 12370 Rev 8 83/324 Figure 34. Watchdog block diagram The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WDGCR register must be between FFh and C0h (see Figure 35): ● Enabling the watchdog: when Software Watchdog is selected (by option byte), the watchdog is disabled after a reset. It is enabled by setting the WDGA bit in the WDGCR register, then it cannot be disabled again except by a reset. When Hardware Watchdog is selected (by option byte), the watchdog is always active and the WDGA bit is not used. ● Controlling the downcounter: this downcounter is free-running: It counts down even if the watchdog is disabled. When the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset. The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see Figure 35). The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WDGCR register (see Figure 36). The window register (WDGWR) contains the high limit of the window: To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 3Fh. Figure 37 describes the window watchdog process. Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). ● Watchdog Reset on Halt option: if the watchdog is activated and the watchdog reset on halt option is selected, then the HALT instruction will generate a Reset. RESET WDGA 6-BIT DOWNCOUNTER (CNT) T6 T0 WATCHDOG CONTROL REGISTER (WDGCR) T1 T2 T3 T4 T5 - W6 W0 WATCHDOG WINDOW REGISTER (WDGWR) W1 W2 W3 W4 W5 comparator T6:0 > W6:0 CMP = 1 when Write WDGCR WDG PRESCALER DIV 4 fOSC2 12-BIT MCC RTC COUNTER MSB LSB DIV 64 0 5 6 11 MCC/RTC TB[1:0] bits (MCCSR Register) |
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