 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
TP3064 数据表(PDF) 7 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
TP3064 数据表(HTML) 7 Page - National Semiconductor (TI) |
|
|
7 / 18 page  Timing Specifications Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC ea50V g5% VBB eb50V g5% TA e 0 Cto70 C by correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests andor product design and characterization All signals are referenced to GNDA Typicals specified at VCC e a 50V VBB eb50V TA e 25 C All timing parameters are measured at VOH e 20V and VOL e 07V See Definitions and Timing Conventions section for test methods information Symbol Parameter Conditions Min Typ Max Units 1tPM Frequency of Master Clock 1536 MHz 1544 MHz MCLKX and MCLKR 2048 MHz tRM Rise Time of Master Clock MCLKX and MCLKR 50 ns tFM Fall Time of Master Clock MCLKX and MCLKR 50 ns tPB Period Bit of Clock 485 488 15725 ns tRB Rise Time of Bit Clock BCLKX and BCLKR 50 ns tFB Fall Time of Bit Clock BCLKX and BCLKR 50 ns tWMH Width of Master Clock High MCLKX and MCLKR 160 ns tWML Width of Master Clock Low MCLKX and MCLKR 160 ns tSBFM Set-Up Time from BCLKX High 100 ns to MCLKX Falling Edge tSFFM Set-Up Time from FSX High Long Frame Only 100 ns to MCLKX Falling Edge tWBH Width of Bit Clock High 160 ns tWBL Width of Bit Clock Low 160 ns tHBFL Holding Time from Bit Clock Long Frame Only 0 ns Low to Frame Sync tHBFS Holding Time from Bit Clock Short Frame Only 0 ns High to Frame Sync tSFB Set-Up Time for Frame Sync Long Frame Only 80 ns to Bit Clock Low tDBD Delay Time from BCLKX High Loade150 pF plus 2 LSTTL Loads 0 180 ns to Data Valid tDBTS Delay Time to TSX Low Loade150 pF plus 2 LSTTL Loads 140 ns tDZC Delay Time from BCLKX Low to 50 165 ns Data Output Disabled tDZF Delay Time to Valid Data from CLe0 pF to 150 pF 20 165 ns FSX or BCLKX Whichever Comes Later tSDB Set-Up Time from DR Valid to 50 ns BCLKRX Low tHBD Hold Time from BCLKRX Low to 50 ns DR Invalid tSF Set-Up Time from FSXR to Short Frame Sync Pulse (1 Bit Clock 50 ns BCLKXR Low Period Long) tHF Hold Time from BCLKXR Low Short Frame Sync Pulse (1 Bit Clock 100 ns to FSXR Low Period Long) tHBFI Hold Time from 3rd Period of Long Frame Sync Pulse (from 3 to 8 Bit 100 ns Bit Clock Low to Frame Sync Clock Periods Long) (FSX or FSR) tWFL Minimum Width of the Frame 64k Bits Operating Mode 160 ns Sync Pulse (Low Level) 7 |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
